You will be joining the FPGA Design Team and contributing modules to a library that is used across our product range.  Experience with the cocotb Python library is desirable. 
You will be required to write timing constraints, understand timing reports and where necessary, modify designs to close timing. 
 
We work with hardware, software and mechanical engineers to bring new products to market.
 
Required Skills & Experience

• SystemVerilog.
• Python.
• RTL verification.
• Writing timing constraints and ensuring these are met.
• Design for low power.
• Writing module specifications and reviewing drafts.
• Code and documentation review. 
• Writing code for a library to a company coding standard.

 
The role requires familiarity with:
 

• The Linux command line.
• Version control software (SVN or Git).
• Markdown

 
 Personal Attributes
 
Committed to engineering best practices in FPGA code development. Able to work effectively within an established team, following existing frameworks and contributing to the continuous improvement of team capabilities.

• Flexible working is considered with work from home up to 3 days per week. 
• Involvement in cutting-edge imaging technologies.
• Collaborative working environment with strong technical expertise.
• Training and career development opportunities.
• Competitive salary and benefits package.